Recently, high-electron-mobility transistors (HEMTs) have attracted attention as ultrafast transistors for communication applications. HEMTs are transistors capable of operating in the millimeter-wave band (30 to 300 GHz), the submillimeter-wave band (300 GHz to 3 THz), and the terahertz band (0.1 to 10 THz).
The total delay time τtotal, which corresponds to the operating speed of HEMTs, is the reciprocal of the cutoff frequency fT and is expressed as the sum of the intrinsic delay time τint and the extrinsic (parasitic) delay time τext, as follows:τtotal=1/(2πfT)=τint+τext 
The intrinsic delay time τint is expressed as follows:τint=Lg/V 
where Lg is the gate length, and v is the average channel electron velocity under the gate electrode.
Hence, a decrease in gate length Lg and an increase in channel electron velocity v result in a faster HEMT with reduced intrinsic delay time τint. An increase in channel electron velocity may be achieved using a semiconductor with a small effective electron mass for the channel. Examples of semiconductors with small effective electron masses include InAs (0.022m0), InSb (0.014m0), and a mixture thereof, namely, InAsSb (where m0 is the electron rest mass).
The extrinsic (parasitic) delay time τext is expressed as follows:τext=ΔL/v+Cgd(Rs+Rd)+τcc 
where ΔL is the increase in effective gate length due to the increase in the length of the depletion layer, Cgd is the gate-to-drain capacitance, Rs (Rd) is the source (drain) resistance, and τcc is the channel charging time. One effective approach to reducing the extrinsic (parasitic) delay time τext is to decrease the source (drain) resistance Rs (Rd).
A typical method for decreasing Rs (Rd) is to reduce the source-to-gate distance Lsg or the gate-to-drain distance Lgd. A reduction in gate-to-drain distance Lgd affects the electric field intensity between the gate and the drain and the gate-to-drain capacitance Cgd. In contrast, a reduction in source-to-gate distance Lsg allows for a nearly proportional decrease in resistance. Recently, however, the source-to-gate distance Lsg has already been significantly reduced, and a method that is more effective than reducing the source-to-gate distance Lsg is becoming increasingly desirable.
Another typical method for decreasing Rs (Rd) is to reduce the source-to-drain distance Lsd. Recently, the intrinsic delay time τint has been reduced because of technical improvements such as the reduction in gate length Lg and the use of semiconductors with small effective electron masses for the channel, and the extrinsic (parasitic) delay time τext has accounted for a larger proportion of the total delay time τtotal. Accordingly, it is desirable to reduce both the intrinsic delay time τint and the extrinsic (parasitic) delay time τext to provide a faster HEMT. Recently, however, the source-to-drain distance Lsd has also been significantly reduced, and a method that is more effective than reducing the source-to-drain distance Lsd is becoming increasingly desirable.
The influence of the parasitic delay time on the delay time has relatively increased due to the reduction in gate length. Accordingly, it is desirable to reduce the extrinsic (parasitic) delay time τext as well as the intrinsic delay time τint to provide a faster HEMT. As discussed above, decreasing the source resistance Rs is effective in reducing the extrinsic (parasitic) delay time τext.
The followings are reference documents.
[Document 1] Japanese Laid-open Patent Publication No. 2006-5380,
[Document 2] Japanese Laid-open Patent Publication No. 2009-60043, and
[Document 3] Japanese Laid-open Patent Publication No. 2005-252276.